Recent advances in the miniaturization of integrated circuits have led to smaller chip areas available for devices. High density dynamic random access memory chips (DRAMs), for example, leave little room for the storage node of a memory cell. Yet, the storage node (capacitor) must be able to store a certain minimum charge, determined by design and operational parameters, to ensure reliable operation of the memory cell. It is thus increasingly important that capacitors achieve a high stored charge per unit of chip area occupied.
Traditionally, capacitors integrated into memory cells have structures based on the parallel plate capacitor. A layer of dielectric is disposed between two conductive layers and the layers are patterned, either sequentially during deposition or all at once. The patterned dielectric layer becomes the capacitor dielectric while the patterned conductive layers become the top and bottom plates or electrodes of the resultant capacitor structure. The charge stored on the capacitor is proportional to the capacitance (C) of the capacitor, C=K K0 A/d, where K is the dielectric constant of the capacitor dielectric, K0 is the vacuum permittivity, A is the electrode area, and d is the spacing between electrodes.
Several techniques have been developed to increase the total charge capacity of the cell capacitor without significantly affecting the chip area occupied by the cell. These include increasing the effective surface area (A) of the electrodes by creating folding structures, such as trench or stacked capacitors. Such structures better utilize the available chip area by creating three-dimensional shapes to which the conductive electrodes and interlayer dielectric conform.
One common way to increase the surface area of the capacitor electrodes employs a roughened or texturized electrode surface. U.S. Patent Application Publication 2003/0003697 to Agarwal et al. (the entirety of which is incorporated by reference), for example, suggests a roughened electrode surface that may comprise annealed ruthenium oxide. More conventionally, roughened polycrystalline silicon (commonly referred to as “polysilicon,” or simply “poly”) in the form of hemispherical grained polysilicon (commonly referred to as “HSG silicon” or “HSG polysilicon”) has been used for a number of years as the bottom or storage electrode of microelectronic capacitors. Such bottom electrodes are commonly in contact with an active area of a silicon substrate that comprises part of a transistor. A thin dielectric layer is formed atop the bottom electrode and typically conforms reasonably well to the rough electrode surface. A top electrode may be deposited on the dielectric layer. The conformality of the dielectric layer commonly provides the outer surface of the dielectric layer with a roughened surface as well. The use of a rough bottom electrode, e.g., a layer of HSG polysilicon, thus effectively increases the electrode area (A in the capacitance formula above), which increases the capacitance of the capacitor structure.
As a bottom electrode for a capacitor, however, roughened polysilicon is typically doped for conductivity to allow the bottom electrode to hold the requisite amount of charge. Unfortunately, rough polysilicon deposition techniques, such as HSG vacuum annealing, are most effective at lower doping levels. Further doping the polysilicon of the bottom electrode tends to result in diffusion of the dopants through the bottom electrode to the underlying active area of the substrate. For example, phosphorus from solid source P2O5, a commonly employed dopant, diffuses easily through silicon during high temperature anneal steps. Downwardly diffused dopants can interfere with junction operation by changing the dopant profile of the active area and the transistor characteristics. Although some implanted dopants, such as arsenic ions, tend to diffuse more slowly, they may fail to adequately dope vertical surfaces, are often unduly expensive, and generally do not entirely eliminate the diffusion problem.
Some have proposed depositing an electrically conductive layer on top of a HSG silicon bottom electrode. For example, U.S. Pat. No. 6,211,033, issued to Sandhu et al. (the entirety of which is incorporated herein by reference), suggests depositing a layer of titanium nitride or titanium carbonitride on the outer surface of an HSG silicon electrode. The use of such a conductive overcoat can lead to greater conductivity in the bottom electrode with less doping of the HSG silicon layer and decreased diffusion of dopants. Such a titanium nitride or titanium carbonitride layer can also serve as an interface for high-stress locations in the HSG silicon layer, reducing the risk of cracking of the dielectric layer and the resultant current leakage. This Sandhu et al. patent suggests forming the titanium nitride or titanium carbonitride layer by metal organic chemical vapor deposition (MOCVD) employing tetrakis(dimethylamido)titanium (TDMAT) and a nitrogen carrier gas, or by CVD with a titanium halide, e.g., TiCl4, as the titanium source and ammonia as the nitrogen source. Both of these CVD techniques can introduce significant levels of impurities in the resultant titanium nitride or titanium carbonitride film. Using MOCVD can incorporate carbon as an impurity in the form of titanium carbide. If the titanium nitride layer is instead deposited using titanium chloride and ammonia, chlorine atoms from the TiCl4 can be incorporated in the deposited material and diffuse into the silicon.